GENERAL INFORMATION
1. Gender
ASSESSMENT OF KNOWLEDGE
A rating of 5 means that you have fully mastered the topic. A rating 1 means that you have no knowledge of topic.
1. Asses your knowledge of creating simple digital circuit in VHDL language which realize basics operations with using of logic functions
2. Assess your knowledge of the use of ISE WebPack tools to simulate a project created in VHDL at the stage of synthesis and implementation in target chip
3. Assess your knowledge of the use of process statements with adequate of signal sensitivity list
4. Assess your knowledge of the use of conditional statements, signals and variables to divide the clock frequency
5. Assess your knowledge of creating a simple state machine in VHDL
6. Assess your knowledge of creating a shift registers in VHDL
7. Assess your knowledge of implementing BCD to seven segment diaplsy with using “case-when”clause
8. Assess your knowledge of the use of counters for counting number of pulses (in example number of pulses generate by button)
9. Assess your knowledge of the use of Digital Clock Manager (DCM) and Block RAM memories
10. Using an FPGA to generate signals
SKILLS
1. Assess how well you can implement a simple digital system with using VHDL language and FPGA devices (in example: a system that performs logical functions, combinational logic)
2. Assess how well you can implement a moderately complex digital system with using VHDL language and FPGA devices (in example: counter integrated with BCD to 7-segment decoder and frequency divider, shifter registers, state machines)
3. Assess how well you can implement a very complex digital system using VHDL language and FPGA devices (in example: implementation of signal generator for the VGA interface with image storage memory)
4. Assess how well you can create test vectors (testbench) and use Xilinx ISE Webpack tools to simulate the design
5. Assess your general knowledge of VHDL and FPGA digital circuit design