library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcdto7seg is 
port
(
	BCD: in std_logic_vector(3 downto 0);
	SSEG: out std_logic_vector(7 downto 0);
	EN : out std_logic_vector(2 downto 0)
);
end bcdto7seg;

architecture Behavioral of bcdto7seg is
signal BCD_temp : std_logic_vector(3 downto 0);
begin
EN <= "110";
BCD_temp <= not BCD;
process(BCD_temp)
begin
	case BCD_temp is
		--------------------abcdefgp
		when "0000"=>SSEG<="00000011";
		when "0001"=>SSEG<="10011111";
		when "0010"=>SSEG<="00100101";
		when "0011"=>SSEG<="00001101";
		when "0100"=>SSEG<="10011001";
		when "0101"=>SSEG<="01001001";
		when "0110"=>SSEG<="01000001";
		when "0111"=>SSEG<="00011111";
		when "1000"=>SSEG<="00000001";
		when "1001"=>SSEG<="00001001";
		when others=>SSEG<="11111111";
end case;
end process;
end Behavioral;