library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cntmod10 is
port
(
	CLK : in std_logic;
	SSEG : out std_logic_vector(7 downto 0);
	EN : out std_logic_vector(2 downto 0)
);
end cntmod10;

architecture Behavioral of cntmod10 is
	signal clk_1Hz : std_logic:='0';
	signal counter : std_logic_vector(3 downto 0):="0000";
	
begin

EN <= "110";

process(CLK)
	  variable clock_cnt : integer:=0;
begin
	  if rising_edge(CLK) then
			if clock_cnt < 6000000 then
				 clock_cnt := clock_cnt+1;
			else
				 clock_cnt := 0;
				 clk_1Hz <= not(clk_1Hz);
			end if;
	  end if;
end process;
	 
process(clk_1Hz)
begin
	  if rising_edge(clk_1Hz) then
			if counter < 10 then
				 counter <= counter + 1;
			else
				 counter <= "0000";
			end if;
	  end if;    
end process;
	 
process(counter)
begin
	case counter is
		--------------------abcdefgp
		when "0000"=>SSEG<="00000011";
		when "0001"=>SSEG<="10011111";
		when "0010"=>SSEG<="00100101";
		when "0011"=>SSEG<="00001101";
		when "0100"=>SSEG<="10011001";
		when "0101"=>SSEG<="01001001";
		when "0110"=>SSEG<="01000001";
		when "0111"=>SSEG<="00011111";
		when "1000"=>SSEG<="00000001";
		when "1001"=>SSEG<="00001001";
		when others=>SSEG<="11111111";
	end case;
end process;
	 
end Behavioral;