library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity higher_freq is
    port ( CLK : in  std_logic;
           LED : out  std_logic);
end higher_freq;

architecture Behavioral of higher_freq is

COMPONENT dcm_instance
PORT(
	CLKIN_IN : IN std_logic;          
	CLKFX_OUT : OUT std_logic;
	CLKIN_IBUFG_OUT : OUT std_logic;
	CLK0_OUT : OUT std_logic
	);
END COMPONENT;

signal clk_50MHz : std_logic := '0';
signal clk_1Hz : std_logic := '0';

begin

process(clk_50MHz)
variable counter_1 : integer := 0;
begin
	if rising_edge(clk_50MHz) then
		if counter_1 < 25000000 then
			counter_1 := counter_1 + 1;
		else
			counter_1 := 0;
			clk_1Hz <= not clk_1Hz;
		end if;
	end if;
end process;

LED <= clk_1Hz;
DCM1 : dcm_instance port map(CLKIN_IN => CLK , CLKFX_OUT => clk_50MHz);

end Behavioral;