-------------------------------------------------------
-- Design Name : one_hot_cnt
-- File Name   : one_hot_cnt.vhd
-- Function    : 8-bit ring counter
-------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;

entity one_hot_cnt_divider is
    port (
        cout 	: out std_logic_vector (7 downto 0); -- output of the counter
        enable : in  std_logic;                    -- enable input
        clk 	: in  std_logic;                       -- clock input
        reset  : in  std_logic                     -- reset input
    );
end entity;

architecture behavioral of one_hot_cnt_divider is 
    signal count : std_logic_vector (7 downto 0):="00000001"; 
	 signal clk_1Hz : std_logic:='0';
begin 
	 process(clk)
		  variable pulse_cnt : integer:=0;
	 begin
		 if (rising_edge(clk)) then
           if (pulse_cnt < 6000000) then
                    pulse_cnt := pulse_cnt + 1;
                else 
                    pulse_cnt := 0;
                    clk_1Hz <= not clk_1Hz; 
                end if;
            end if;
	 end process;
    process(clk_1Hz) 
	 begin
        if (rising_edge(clk_1Hz)) then 
            if (reset = '0') then 
                count <= "00000001"; 
            elsif (enable = '0') then 
                count <= (count(6) & count(5) & count(4) & count(3) & count(2) & count(1) & count(0) & count(7)); 
            end if;
        end if;
    end process;
    cout <= count;
end architecture;