--VGA signal generator with resolution 640x480

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity animation_vga is

port( 
		clk      		: in std_logic;	
		hsync,vsync  	: out std_logic;					        
		red 			   : out std_logic_vector(2 downto 0);	  
		green 		   : out std_logic_vector(2 downto 0);	  
		blue  		   : out std_logic_vector(1 downto 0)	  
);
end animation_vga;

architecture behavioral of animation_vga is

component dcm_inst
	port(
		CLKIN_IN : IN std_logic;          
		CLKFX_OUT : OUT std_logic
		);
end component;

constant h_max : std_logic_vector(9 downto 0) := conv_std_logic_vector(799,10); -- 799 max number of pixels (640 + additional pixels for synchronization)
constant v_max : std_logic_vector(9 downto 0) := conv_std_logic_vector(524,10); -- 524 max number of lines (480 + additional lines for synchronization)

signal clk_25 			: std_logic;
signal clk_60hz 		: std_logic;
signal video_out		: std_logic_vector(7 downto 0);
signal hcnt, vcnt		: std_logic_vector(9 downto 0) := "0000000000";

signal offset_x : std_logic_vector(7 downto 0):="00000000";
signal offset_y : std_logic_vector(7 downto 0):="00000000";

BEGIN

-- process with drawing rectangle on the screen
rectangle: process(hcnt, vcnt)
begin
	if hcnt <= (300+offset_x)  and hcnt >= (200+offset_x) and vcnt >= (200+offset_y) and vcnt <= (300+offset_y) then
		video_out<="11111111";
	else
		video_out<="00000000";
	end if;
end process;

--R (3 bits) G (3 bits) and B (2 bits) outputs on the VGA screen
red   <= video_out(7 downto 5);
green <= video_out(4 downto 2);
blue  <= video_out(1 downto 0);

-- 60 Hz
process(clk_25)	-- 60 Hz clock generator
variable licznik : integer range 0 to 1000000;
begin
   if rising_edge(clk_25) then 
		licznik:=licznik+1;
		if licznik>=416667 then
			licznik:=0;
			clk_60hz<=not(clk_60hz);
		end if;
	end if;
end process;

animation: process(clk_60hz) -- animation of rectangle
begin	
	if rising_edge(clk_60hz) then
		offset_x<=offset_x+"00000001";
		offset_y<="00000000";
		if offset_x>=50 then
			offset_x<="00000000";
		end if;
	end if;
end process;


-- VGA synchronization signal generator
vga_generator: process(clk_25)

begin

if (clk_25'event and clk_25 = '1') then

-- hcnt signal counts number of pixels (640 + additional pixels for synchronization)
	if (hcnt >= h_max) then
		hcnt <= "0000000000";
	else
		hcnt <= hcnt + "0000000001";
	end if;

-- generator of horizontal synchronization signal 
	if (hcnt >= 656) and (hcnt <= 751) then
		hsync <= '0';
	else
		hsync <= '1';
	end if;

-- vcnt signal counts number of lines in vertical direction (480 + additional lines for synchronization)
	if (vcnt >= v_max) and (hcnt >= 799) then
		vcnt <= "0000000000";
	else 
		if (hcnt = 799) then
			vcnt <= vcnt + "0000000001";
		end if;
	end if;

-- generator of vertical synchronization signal
	if (vcnt >= 490) and (vcnt <= 491) then
		vsync <= '0';
	else
		vsync <= '1';
	end if;
	
end if;
end process vga_generator;

DCM1 : dcm_inst port map(CLKIN_IN => clk , CLKFX_OUT => clk_25); -- assignement of DCM ports to internal signals in the architecture

END behavioral;