library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lfsr4bit is
  port (
	 rst : in std_logic;
    clk : in  std_logic; 
    rand   : out std_logic_vector(3 downto 0)  -- LFSR 
  );
end entity;

architecture Behavioral of lfsr4bit is
  signal lfsr 	    : std_logic_vector (3 downto 0); -- LFSR register
  signal feedback  : std_logic;                     -- LFSR feedback
  signal clk_1Hz 	 : std_logic;

begin

  feedback <= not(lfsr(3) xor lfsr(2));	-- feedback by polynomial x^3+x^2+1
  
  process(clk)
	 variable counter : integer:=0;
  begin
	 if (rising_edge(clk)) then
      if (counter>6000000) then
        counter:=0; 
		  clk_1Hz <= not clk_1Hz;
      else
        counter:=counter+1;
      end if;
    end if;
  end process;
  
  lfsr_pr : process (clk_1Hz) 
	begin
    if (rising_edge(clk_1Hz)) then
      if (rst = '0') then
        lfsr <= (others=>'0');
      else
        lfsr <= lfsr(2 downto 0) & feedback;
      end if;
    end if;
  end process lfsr_pr;
  rand <= lfsr;	-- parallel output of LFSR

end architecture;