library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.ALL;
    
entity tb_lfsr4bit is
end entity;

architecture test of tb_lfsr4bit is

  constant PERIOD  : time   := 83.3 ns;--frequency 12MHz
  signal clk       : std_logic := '0';
  signal rst      : std_logic := '0';
  signal rand      : std_logic_vector(3 downto 0);
  signal endSim	   : boolean   := false;

  component lfsr4bit is
    port (
      rst      : in  std_logic;                       
      clk       : in  std_logic;               
      rand      : out std_logic_vector(3 downto 0)   
    );
  end component;

begin
  clk     <= not clk after PERIOD/2;
  rst    <= '1' after  PERIOD*2;
  endSim  <= true after PERIOD*60;

 -- End the simulation
 process 
 begin
   if (endSim) then
     assert false 
       report "End of simulation." 
       severity failure; 
   end if;
   wait until (clk = '1');
 end process;	

 lfsr_inst : lfsr4bit
 port map (
   clk      => clk,
   rst      => rst,
   rand     => rand
 );
end architecture;