--VGA signal generator with resolution 640x480

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity block_ram_vga is

port( 
		clk      		: in std_logic;	
		hsync,vsync  	: out std_logic;					        
		red 			   : out std_logic_vector(2 downto 0);	  
		green 		   : out std_logic_vector(2 downto 0);	  
		blue  		   : out std_logic_vector(1 downto 0)	  
);
end block_ram_vga;

architecture behavioral of block_ram_vga is

--component rom_inst
--  port (
--    clka : IN std_logic;
--    addra : IN std_logic_vector(11 DOWNTO 0);
--    douta : OUT std_logic_vector(7 DOWNTO 0)
--  );
--end component;
--
--component dcm_inst
--	port(
--		CLKIN_IN : IN std_logic;          
--		CLKFX_OUT : OUT std_logic
--		);
--end component;

constant h_max : std_logic_vector(9 downto 0) := conv_std_logic_vector(799,10); -- 799 max number of pixels (640 + additional pixels for synchronization)
constant v_max : std_logic_vector(9 downto 0) := conv_std_logic_vector(524,10); -- 524 max number of lines (480 + additional lines for synchronization)

signal clk_25 			: std_logic;
signal video_out		: std_logic_vector(8 downto 0);
signal hcnt, vcnt	: std_logic_vector(9 downto 0) := "0000000000";

--signals for internal ROM memory created from Block RAM
signal   address: std_logic_vector(11 downto 0); 
signal   clock: std_logic;
signal	data: std_logic_vector(7 downto 0);


begin

--R (3 bits) G (3 bits) and B (2 bits) outputs on the VGA screen
RED <= data(7 downto 5) when ((Hcnt < 64)  and (Vcnt < 64))	else "000"; 
GREEN <= data(4 downto 2) when ((Hcnt < 64) and (Vcnt < 64)) else "000";
BLUE <= data(1 downto 0) when ((Hcnt < 64)  and (Vcnt < 64))	else "00";


clock<=clk_25; --ROM memory and VGA clock

-- synchronizacja wideo
generator_video: process(clk_25)

begin


if (clk_25'event and clk_25 = '1') then

-- hcnt signal counts number of pixels (640 + additional pixels for synchronization)
	if (hcnt >= h_max) then
		hcnt <= "0000000000";
	else
		hcnt <= hcnt + "0000000001";
	end if;

-- generator of horizontal synchronization signal 
	if (hcnt >= 656) and (hcnt <= 751) then
		hsync <= '0';
	else
		hsync <= '1';
	end if;

-- vcnt signal counts number of lines in vertical direction (480 + additional lines for synchronization)
	if (vcnt >= v_max) and (hcnt >= 799) then
		vcnt <= "0000000000";
	else 
		if (hcnt = 799) then
			vcnt <= vcnt + "0000000001";
		end if;
	end if;

-- generator of vertical synchronization signal
	if (vcnt >= 491) and (vcnt <= 492) then
		vsync <= '0';
	else
		vsync <= '1';
	end if;
	
	if Hcnt < 64 and Vcnt < 64 then -- limit data range to size of image
		address(5 downto 0) <= Hcnt(5 downto 0);
		address(11 downto 6) <= Vcnt(5 downto 0);
	end if;
	
end if;
end process GENERATOR_VIDEO;

--ROM1 : rom_inst port map(clock,address,data); -- assignement of memory ports to internal signals in the architecture
--DCM1 : dcm_inst port map(CLKIN_IN => clk , CLKFX_OUT => clk_25); -- assignement of DCM ports to internal signals in the architecture

end behavioral;