library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_reg is
    Port ( din   : in  std_logic;
           clk : in  std_logic;
           led : out std_logic_vector(3 downto 0);
			  q : out std_logic);
end shift_reg;

architecture behavioral of shift_reg is
	 signal clk_1Hz : std_logic := '0';
    signal s_reg : std_logic_vector(3 downto 0) := "0000";
begin

-- clock divider
process (clk)
variable counter : integer := 0;
begin
  if (clk'event and clk = '1') then
		if (counter < 6000000) then
			counter := counter + 1;
		else
			counter := 0;
			clk_1Hz <= not clk_1Hz;
		end if;
  end if;
end process;
    
-- shift register
process (clk_1Hz)
begin
  if (clk_1Hz'event and clk_1Hz = '1') then
		s_reg(2 downto 0) <= s_reg(3 downto 1);
		s_reg(3) <= din;
  end if;
end process;

-- hook up the shift register bits to the LEDs
led <= s_reg;
q <= s_reg(0);

end behavioral;