library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity u_d_cnt is port (
	 clk, res, u_d: in std_logic;
	 q: out std_logic_vector(3 downto 0)
	 );
end u_d_cnt;

architecture a of u_d_cnt is
	signal state: std_logic_vector(3 downto 0);
	constant S0: std_logic_vector(3 downto 0) := "0000";
	constant S2: std_logic_vector(3 downto 0) := "0010";
	constant S4: std_logic_vector(3 downto 0) := "0100";
	constant S6: std_logic_vector(3 downto 0) := "0110";
	constant S8: std_logic_vector(3 downto 0) := "1000";
	constant S10: std_logic_vector(3 downto 0) := "1010";
	constant S11: std_logic_vector(3 downto 0) := "1011";
	constant S12: std_logic_vector(3 downto 0) := "1100";
	constant S13: std_logic_vector(3 downto 0) := "1101";
	constant S14: std_logic_vector(3 downto 0) := "1110";
	constant S15: std_logic_vector(3 downto 0) := "1111";

begin 
process (clk, res) begin
  if (res = '0') then state <= "0000";
	elsif (clk='1' and clk'event) then
		if u_d = '1' then
		 case state is 
			when S0 => state <= S2;
			when S2 => state <= S4;
			when S4 => state <= S6;
			when S6 => state <= S8;
			when S8 => state <= S10;
			when S10 => state <= S11;
			when S11 => state <= S12;
			when S12 => state <= S13;
			when S13 => state <= S14;
			when S14 => state <= S15;
			when others => state <= S0;
		 end case;
		elsif u_d = '0' then
		 case state is 
			when S0 => state <= S15;
			when S2 => state <= S0;
			when S4 => state <= S2;
			when S6 => state <= S4;
			when S8 => state <= S6;
			when S10 => state <= S8;
			when S11 => state <= S10;
			when S12 => state <= S11;
			when S13 => state <= S12;
			when S14 => state <= S13;
			when S15 => state <= S14;
			when others => state <= S0;
		 end case;
		end if;      
	end if;      
 q <= state;
end process;
end;