Hardware Implementat ...

Topic outline

General
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1. Introduction to ISE Webpack. Combinational logic.
2. Testbench and simulation. Frequency divider.
- Laboratory excercise no. 2 - Testbench and simulation. Frequency divider. File
  English version
- Ćwiczenia laboratoryjne nr 2 - Testbench i symulacja. Dzielnik częstotliwości. File
  Polish version
- Video tutorial no. 2 URL
- Files for lab no. 2 Folder
  Teaching aids: VHDL source files for hot-one counter and frequency divider.
3. State machine in VHDL. Shift register.
- Laboratory excercise no. 3 - State machine in VHDL. Shift register. File
  English version
- Laboratorium nr 3 - Automat stanów w VHDL. Rejestr przesuwny. File
  Polish version
- Video tutorial no. 3 URL
- Files for lab no. 3 Folder
  Teaching aids: VHDL source files for state machine and shift register with additional parts.
4. BCD to seven-segment display decoder. Counters.
- Laboratory excercise no. 4 - BCD to seven-segment display decoder. Counters. File
  English version
- Laboratorium nr 4 - Dekoder kodu BCD na kod wyświetlacza siedmio‐segmentowego. Liczniki. File
  Polish version
- Video tutorial no. 4 URL
- Files for lab no. 4 Folder
  Teaching aids: VHDL source files for BCD to seven segment decoder and counter mod 10.
5. Digital Clock Manager (DCM).
- Laboratory excercise no. 5 - Digital Clock Manager (DCM) File
  English version
- Ćwiczenia laboratoryjne nr 5 - DCM - Menedżer (syntezer) sygnałów zegarowych. File
  Polish version
- Video tutorial no. 5 URL
- Files for lab no. 5 Folder
  Teaching aids: VHDL source files with an example of using DCM to increase and decrease the clock frequency.
6. Pseudorandom number generation using LFSR.
- Laboratory excercise no. 6 - Random number generation using LFSR File
  English version
- Ćwiczenia laboratoryjne nr 6 - Generowanie liczb pseudolosowych przy użyciu rejestru LFSR. File
  Polish version
- Video tutorial no. 6 URL
- Files for lab no. 6 Folder
  Teaching aids: VHDL source files for random number generator with LFSR (testbench is included).
7. Incremental encoder.
- Laboratory excercise no. 7 - Incremental encoder. File
  English version
- Ćwiczenia laboratoryjne nr 7 - Enkoder inkrementalny. File
  Polish version
- Video tutorial no. 7 URL
- Files for lab no. 7 Folder
  Teaching aids: VHDL source files for decoder of encoder signals.
8. Video signal generator (VGA interface).
- Laboratory excercise no. 8 - Video signal generator (VGA interface). File
  English version
- Ćwiczenia laboratoryjne nr 8 - Generator sygnału wideo (interfejs VGA). File
  Polish version
- Video tutorial no. 8 URL
- Files for lab no. 8 Folder
  Teaching aids: VHDL source files for VGA signal generator with 2 similar examples, binary files for FPGA programming.
9. Block RAM memory in FPGA - example of use.
- Laboratory excercise no. 9 - Block RAM memory in FPGA ‐ example of use. File
  English version
- Ćwiczenia laboratoryjne nr 9 - Wykorzystanie pamięci blokowej RAM w układzie FPGA. File
  Polish version
- Video tutorial no. 9 URL
- Files for lab no. 9 Folder
  Teaching aids: VHDL source files, graphic files in BMP format, Matlab script, binary files for FPGA programming.
10. PicoBlaze 8-bit microcontroller.
- Laboratory excercise no. 10 - PicoBlaze 8-bit microcontroller. File
  English version
- Ćwiczenia laboratoryjne nr 10 - 8-bitowy mikrokontroler PicoBlaze File
  Polish version
- Video tutorial no. 10 URL
- Files for lab no. 10 Folder
  Teaching aids: VHDL source files, PicoBlaze assembler files, binary files for FPGA programming.
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